Heterogeneous System Architecture on STM32MP1: A Dual-Core GNSS/INS & Edge Automation Platform (PoC)
Why a standard MCU was not enough and we chose STM32MP1
This case study demonstrates how a heterogeneous microprocessor architecture (STM32MP1) solves a common hardware engineering dilemma: delivering industrial-grade Linux connectivity, enterprise security, and web management while maintaining microsecond-level deterministic sensing on a single silicon die.
Developed by WizzDev as a proof of concept, the system serves as an IP-owned, multi-sensor position, heading, and time synchronization engine for agricultural machinery automation.
Note: This is a reference AI-generated image, not a physical PoC.
Note: This is a reference AI-generated image, not a physical PoC.
Project Context
This case study demonstrates how a heterogeneous microprocessor architecture (STM32MP1) solves a common hardware engineering dilemma: delivering industrial-grade Linux connectivity, enterprise security, and web management while maintaining microsecond-level deterministic sensing on a single silicon die.
Developed by WizzDev as a proof of concept, the system serves as an IP-owned, multi-sensor position, heading, and time synchronization engine for agricultural machinery automation.
Hardware & Software Stack Overview
Why a standard MCU was not enough and we chose STM32MP1
When designing standalone sensor controllers, the first choice for engineering teams are in most cases high-performance microcontrollers such as the STM32H7/F7 series, NXP i.MX RT1060/1170, or even an ESP32-S3. If the requirements were strictly to read GNSS data, run an EKF with an IMU, and broadcast positions over CAN FD or UART, any of these MCUs would be sufficient.
However, the complete product requirements introduced competing engineering demands:
High-Level Application Domain
Rich web-based configuration interfaces, encrypted telemetry pipelines over Ethernet/Cellular, robust file systems, and resilient over-the-air (OTA) dual-bank update capabilities.
Deterministic Real-Time Domain
Hard real-time sensor sampling (100 Hz IMU/GNSS fusion), sub-microsecond 1PPS hardware timestamping, and zero-jitter control loops.
Security & IP Protection
On-chip hardware key storage, signed boot chains, and a Trusted Execution Environment (TEE) to protect firmware against reverse engineering and machine theft.
Accomplishing this with standard microcontrollers would require a two-chip architecture (e.g., an application processor running Linux paired with an external real-time MCU over SPI or UART). That approach introduces extra board-to-board latency, complex IPC protocols, larger PCB footprints, and higher bill-of-materials (BOM) costs.
The STM32MP1 architecture: Single-SoC domain separation
The dual Cortex-A7 + Cortex-M4 architecture of the STM32MP1 eliminated the need for a secondary controller, allowing us to enforce strict domain separation on a single piece of silicon.
Separation of Concerns (Linux vs. Real-Time)
Cortex-A7 Domain (Rich Execution Environment)
Runs a custom Yocto-based Linux distribution. It handles non-deterministic, high-bandwidth tasks: network socket management, web-based field diagnostic interfaces, telemetry streaming, system logging, and OTA update execution.
Cortex-M4 Domain (Microcontroller Execution Environment)
Executes a deterministic FreeRTOS environment (or bare-metal loop) dedicated entirely to timing-critical sensor polling, UBX message parsing, and high-rate matrix operations for sensor fusion.
Zero-latency inter-core communication (OpenAMP / RPMsg)
Data exchange between the Linux user space and the real-time core utilizes the OpenAMP framework over RPMsg (Remote Processor Messaging) operating on shared RAM.
- The Cortex-M4 processes raw IMU and GNSS feeds, executes fusion maths, and pushes clean navigation vectors and status flags to shared memory buffers.
- The Cortex-A7 consumes these pre-processed streams without taxing its CPU or interrupting real-time M4 execution cycles.
Native Peripheral Density without Bridge Chips
The SoC integrates the entire required interface suite directly, eliminating external bridge microcontrollers, interface converters, or multiplexers:
- Dual CAN FD controllers for ISOBUS and vehicle bus integration.
- Gigabit Ethernet MAC with hardware IEEE 1588 timestamping for system timing.
- Multiple native UART/USART channels for legacy terminal communication and raw GNSS parsing.
- Battery-backed RTC and hardware timer capture/compare pins for 1PPS distribution.
Enterprise-Grade Hardware Security
Guidance hardware is a high-value theft target. The STM32MP1’s built-in TrustZone / TEE (TF-A, OP-TEE), combined with hardware cryptographic keys and secure boot, ensures that firmware cannot be extracted, cloned, or modified even if the unit is physically removed from the machine.
Application workload: GNSS/INS & timing engine
To demonstrate the capabilities of this architecture, the platform was deployed as a standard-precision, high-reliability guidance and timing core for agricultural machinery operating in GPS-denied environments.
Overcoming signal dropouts in software
Agricultural machinery routinely operates along tree lines, beside silos, and on steep slopes where roof-mounted antennas experience severe pitch/roll offsets. Rather than specifying expensive multi-band RTK hardware, the hard work was handled in software on the Cortex-M4:
Multi-Constellation Integration
A standard-precision u-blox NEO-M9N module streams raw data across concurrent constellations (GPS, GLONASS, Galileo, BeiDou).
Real-Time Sensor Fusion & Slope Compensation
The M4 core pairs GNSS feeds with an industrial 9-axis IMU to dynamically calculate and compensate for antenna offsets on slopes up to 30, while coasting through temporary satellite outages.
Active Integrity Monitoring
The M4 continually cross-checks satellite updates against physical IMU accelerations and CAN-bus wheel speed odometry. Discrepancies or spoofing/jamming signals trigger immediate system flags rather than allowing position drift.
Centralized 1PPS Time Server
Using the STM32MP1 Ethernet MAC hardware-timestamping capabilities, the unit acts as the master clock reference for onboard camera systems and section controllers, distributing time via NTP/PTP and a differential hardware 1PPS signal.
Key Takeaways
To demonstrate the capabilities of this architecture, the platform was deployed as a standard-precision, high-reliability guidance and timing core for agricultural machinery operating in GPS-denied environments.
Overcoming signal dropouts in software
Agricultural machinery routinely operates along tree lines, beside silos, and on steep slopes where roof-mounted antennas experience severe pitch/roll offsets. Rather than specifying expensive multi-band RTK hardware, the hard work was handled in software on the Cortex-M4:
Multi-Constellation Integration
A standard-precision u-blox NEO-M9N module streams raw data across concurrent constellations (GPS, GLONASS, Galileo, BeiDou).
Real-Time Sensor Fusion & Slope Compensation
The M4 core pairs GNSS feeds with an industrial 9-axis IMU to dynamically calculate and compensate for antenna offsets on slopes up to 30, while coasting through temporary satellite outages.
Active Integrity Monitoring
The M4 continually cross-checks satellite updates against physical IMU accelerations and CAN-bus wheel speed odometry. Discrepancies or spoofing/jamming signals trigger immediate system flags rather than allowing position drift.
Centralized 1PPS Time Server
Using the STM32MP1 Ethernet MAC hardware-timestamping capabilities, the unit acts as the master clock reference for onboard camera systems and section controllers, distributing time via NTP/PTP and a differential hardware 1PPS signal.